ODDAQ.HTML
1 March, 1995, rev 3/1/95, RJW
DAQ for the SuperKamiokande Outer Detector.
Ken Young, Jeff Wilkes, Andrew Stachyra, Hans Berns
University of Washington
Table of Contents.
1. Introduction.
2. Hardware
3. Software.
4. SuperK Acronym Dictionary
1. Introduction.
The purpose of the Outer Detector DAQ system is to record the arrival times and characteristics of PMT pulses associated with events in the SuperK detector. An independent DAQ system is being constructed by the Japanese side of the collaboration for the inner detector. For the OD system, the desiderata are:
1.1 Input to the DAQ
1.2 TDC
1.3 ADC
1.4 Trigger and Gates.
1.5 Dead time.
After a trigger is issued to a crate of ADCs and TDCs, the digitization of the signal into a buffer will cause a deadtime. The TDC deadtime is quite short [usually less than 1 microsec and depends on the number of hits per module]. The ADC deadtime is quite a bit longer at 12 micro sec.
1.6 Readout of data.
After digitization, the data buffered in the individual TDC/ADC modules will be readout to a very large VME buffer memory. This system will be data driven. At intervals of approximately 5 seconds the VME buffer memory will be toggled to the VME bus. A paired VME memory will be toggled to the TDC/ADC access. This is called ping-pong dual port memory. In this way, the memory toggled to the FB will be data driven. A schematic view of the ping-pong scheme can be found here. The memory toggled to the vme bus will be read by the VME controller. The VME controller (Outer Detector Host CPU) will be a SUN Classic or equivalent with a large buffer memory and a connection via FDDI and data concentrators to the Main Host event builder in the Central Detector. See section 1.7 for a figure showing this arrangement.
The FB to VME memory loop will be data driven. The VME memory to SUN memory will be driven by the SUN. The SUN to host event builder will be driven by the HOST. These three processes will necessarily run asynchronously so that large buffering is required at the interchanges.
1.7 Merging data streams with the Inner Detector.
The 12,000 PMTs of the ID will be digitized by the specially designed ATM modules and will be buffered by VME ping pong dual port memories as well. It is expected that the toggling will occur approximately at the same time for the ID and OD DAQ. In this way the complete events wil be assembled by the host event builder by picking the proper event from the SUN buffers. The OD and ID event data will be identified by event numbers which have been commonly generated in the TRG module. A figure showing the schematic of the FDDI and concentrator flow chart is shown here. A description of the FDDI product line can be found here. The sunlink software utilizing the FDDI card can be found here.
2. Hardware
2.1 Overview.
The central part of the OD DAQ hardware is comprised of Lecroy 1877 pipeline TDCs and Lecroy 1881M ADCs which will reside in fast bus (FB) crates. The crate is controlled by a fast-bus-smart- crate-controller (FSCC). There will be one FB crate in each of the quadrant counting houses. One quarter of the OD PMTs will feed into each quadrant counting house. The data from each FB crate will feed into a central counting house. The central counting house will have the VME buffer memory for all the qudrants in one VME crate.
2.1 Front End.
The PMT signals arriving at the quadrant CH will plug into a 12 channel Paddle Board. The function of the paddle board is to supply the PMT with HV and pick off the PMT signal by capacitive coupling. The signal is sent in turn to a discriminator board. The discriminator board is a custom modified version of the model N277 16 channel board manufactured by Nanometric Systems . The schematic of the circuit is shown here and the specifications are shown here. The SuperK prototype board has been modified to discriminate at 12.5 mV or so threshold and to provide a TOT output pulse in a format (ECL) necessary to input to the TDC. In stage 2, we will have a custom discriminator/splitter/delay board that will feed the ADC as well. An analogue sum of the 16 discriminator channel outputs on each board is put into an output driver that will provide 20 mV/hit (0 to 320 MV) as the HITSUM output. A graph showing the approximately linearity of the HITSUM output is shown here. To assure short cables for quiet operation, the pmt cables, the paddle card and the amp/discriminator must be arranged as shown in cabling .
2.2 The FAST BUS PART
2.2.1 The TDC
The TDCs are Lecroy 1877 digital pipeline TDCs with 0.5 nsec time resolution, 32 microsec wide window and 8 event buffering. The TDC will continuously record hits until a trigger signal stops the pipeline. The hits (rising and falling edges) are buffered with the times calculated relative to the trigger signal. The data for each channel will reside in an 8 event deep FIFO.
2.2.2 The ADCs
The ADCs are Lecroy 1881M ADCs. These will integrate the charge within a gate. This is not a pipeline device, so we must provide a delay for the signal pulses for the time required to form a trigger, which is at least 700 nsec. Therefore, to accomodate the ADCs the discriminator cards must be modified to include a signal splitter and a delay of about 900 nsec; the delay device used must not significantly alter the pulse area over the required pulse height range. The 1881M also has an 8 event deep FIFO buffer.
2.2.3 The Fast Bus Latch.
Each crate will have a 96 channel fast bus latch. This will latch the contemperaneous event number and other useful data. The data structure will be identical to that of the TDCs and ADCs so that we will be guaranteed perfect registration of the data from the various quadrants.
2.2.4 FSCC (Fast bus smart crate controller)
The FSCC commercialy manufactured by Bira has been designed by Fermilab and uses the Vxworks operating system. The FSCC is data driven and will sequentially read-out all the active channels of the TDCs and ADCs. This data is ported to a RS485 output running at up to 10 Mhz with 4 Byte words. The FSCC also has an ethernet I/O. The FSCC control files are ported through the ethernet. The data can also be read out via ethernet for diagnostic purposes. The central processor is a 68020 which provides much needed flexibility for programming and debugging. A detailed Dart library supported at FNAL can be found here.
2.3. The VME part of the data buffering.
The single VME crate for the OD DAQ system will sit in the central counting house. This will house the 4 pairs of dual port memories, the universal time clock, the auxiliary data latches, the local clock, and interfaces to the Sun OD Host computer.
2.3.1 The dual port memory receivers. (DM115/DC-2/VSB)
Function of the dual port memory receiver.
2.3.2 The dual port memory.
This memory has a VME port and a VSB port. Only one port can be active at a time. Memory location must be assigned by a processor on one of the buses. The Fastbus crate will load data through the VSB port, and when a sufficient block is available, the Sun host can download the data through the VME port; meanwhile the other segment of the ping-pong pair can be utilized by the Fastbus crate.
2.4 Universal Time clock and auxiliary data latch
The Universal Time will be recorded for each event trigger. The universal time will be recorded with 1 microsec accuracy. The clock module on the VME bus will be disciplined by IRIG-B time code received via fiber-optic link from the surface GPS receiver. Even though the antenna will be in a mountain valley, so that only a few satellites can be viewed at any one time, the clock function only requires ONE satellite to be visible once the geographical position of the receiver has been determined to sufficient precision. We will also record the event trigger time with a local clock which has accuracy to 20 nsec.
The VME clock interface description is found here.
2.5 VME controller and OD event building.
The VME crate will be controlled by a SUN utilizing the Solaris 2.X operating system. The connection between the VME crate and the SUN will be via the Bit3 interface model 467-1. The Bit3 software will be model 944-1. By booting up with the Bit3 Kernel, the SUN will treat the VME buffers as just other addressable memory.
2.5.1 OD event building hardware
2.5.2 SUN to Host hardware
3 Software.
3.1 FSCC software.
This is being prepared by the UMd/Lasl group.
3.2 DM115/DC-2 software.
This is being prepared by the UMd/Lasl group. We will have a hyperlink for these items when they are available.
3.3 OD Event Building
3.4 Event Size
Each complete OD event will have a header followed by the TDC and ADC information.
The header will be comprised of
The header will be followed by:
The size of the event , determined by the number of PMTs which exceed threhold during the time window of interest. The following table shows the event size.
Sizes of various items in DAQ chain
item no. of bits
event number 32
Universal time 64
local time 32
trigger type 16
busy type 8
total header size 152
TDC channel 32
ADC channel 32
During routine operation, the data rate will be low. The experimental plan is to ping-pong the VME buffer memories in the whole detector every 256 events. The trigger rate is 50 Hz so the ping-pong will occur every 5 seconds.
Event and Buffer Size and rate.
item no.of no. of no. of no. of
Total Total events PMs bits TDC
bits ADC no. of no. of
bits Bytes events per buffer 256
482 K 60 K no. of cosmic 15
100 48 K 48 K 96 K 12 K rays
no. of low
energy 241 25 193 K 193 K 386 K 48 K
events
trigger rate 50 Hz
time for one 5 sec
buffer
The events will be distributed amongst 4 VME dual port memories. When the memories are switched to the VME bus, the SUN will buildl the OD events.
During a super nova in the Milky Way galaxy, the event rate will be 4000 events in 10 seconds. This will be like Cosmic Ray events with 100 struck PMTs. This corresponds to 3.2 MB of data in 10 seconds. This large data rate can be sustained by the FB transfer which has a 120 MB/sec maximum rate. The data can be buffered by the vme dual port memories each of which has a capacity of 32 MB. We will have eight 32 MB memory modules in the vme crate. During this time, the event builder will be very busy so that the individual SUN memories must be large enough to handle the queue. In the event that the SUN system cannot keep up with data transfer, the dpms have the capacity and will meet the demand. The 44 MB of Sun memory reserved for buffering data should be enough for the buffering between the dpms and the host event builder.
3.5 Memory Size in VME
3.6 Memory Size in SUN with OD events.
3.7 Requirements for passage to Host Event Builder
connectivity to FDDI networks. The product provides a single-attach connection to a
FDDI concentrator and also supports FDDI's redundant single-attach configuration for
users who require increased fault-tolerance.
NFS, and supports Station Management (SMT) 6.2, as specified by ANSI X3T9.5.
FDDI/S software includes a SunNet Manager SMT Proxy Agent.
At this time, we are investigating the compatibility of the SUN and Fujitso products and the availability of the Fujitso FDDI card in the U.S.
4. Super-Kamiokande Acronym Dictionary
A list of acronyms used in SuperK is under construction and will be expanded.