UWa Electronics for SuperK: Documentation

This page maintained by RJW; most of content is due to HGB.

BIP (Buffering in Progress) Card: Generates BIP pulse from OR of busy bits on TDCs in each hut, to inhibit triggers and monitor deadtime. Version 1 (currently installed), Version 3 (to be tested at mine).

Block diagram (version 1): bip-blk.ps
PCB Layout (version 1): bip-pcb.ps
PCB Layout (version 3): bip3-sk.ps
BIP card signal timing diagram: bipt-blk.ps

Event Number Splitter Board: distributes event number bits to the Struck latches in the quadrant huts.

Event Number Splitter Board block diagram: ens-blk.ps
Event Number Splitter Board, PCB layout: ens-pcb.ps

Fastbus Power supply manual (includes diagrams): fbmanual.ps
LTC (Local Time Clock) Board: Generates 20 nsec timestamps; UTC is recorded every LT clock rollover.

Block diagram: ltc-blk.ps
PCB Layout artwork: ltc-pcb.ps

Reset Board: Version 1 = backup board, Version 2 = currently installed.

Block diagram (version 1): rst1-blk.ps
PCB Layout diagram (version 1): rst1-pcb.ps
Block diagram (version 2): rst2-blk.ps
PCB Layout diagram (version 2): rst2-pcb.ps

TDC Tester Board: provides time-offset pulses for testing TDCs.

PCB layout diagram: tdct-pcb.ps

List of UWa items currently at SuperK, with models numbers, serial numbers, and property tag numbers: skitems.ps